Datasheet4U Logo Datasheet4U.com

XC95144XL - High Performance CPLD

Datasheet Summary

Features

  • 5 ns pin-to-pin logic delays.
  • System frequency up to 178 MHz.
  • 144 macrocells with 3,200 usable gates.
  • Available in small footprint packages - 100-pin TQFP (81 user I/O pins) - 144-pin TQFP (117 user I/O pins) - 144-CSP (117 user I/O pins) - Pb-free available for all packages.
  • Optimized for high-performance 3.3V systems - Low power operation - 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals - 3.3V or 2.5V output capability - Advanced 0.35 micro.

📥 Download Datasheet

Datasheet preview – XC95144XL

Datasheet Details

Part number XC95144XL
Manufacturer Xilinx
File Size 190.45 KB
Description High Performance CPLD
Datasheet download datasheet XC95144XL Datasheet
Additional preview pages of the XC95144XL datasheet.

📁 Similar Datasheet

  • XC9510 - Synchronous Step-Down DC/DC Converter (Torex Semiconductor)
  • XC9511 - Synchronous Step-Down DC/DC Converter (Torex Semiconductor)
  • XC9515 - 2-channel Synchronous Step-Down DC/DC Converter (Torex)
  • XC9516 - Triple Output Power Supply (Torex)
  • XC9519 - Dual Output Step-Up/Inverting DC/DC Converter (Torex)
  • XC95 - 2ch. Step-up / down DC/DC Controller ICs (Torex Semiconductor)
  • XC9501 - 2ch. Step-up DC/DC Controller (Torex Semiconductor)
  • XC9502 - 2ch. Step-up / down DC/DC Controller ICs (Torex Semiconductor)
  • XC9503 - 2ch Step-down DC/DC Controller (Torex Semiconductor)
  • XC9504 - Step-up / Inverting DC/DC Controller (Torex Semiconductor)
Other Datasheets by Xilinx
  • XC95144XV - High-Performance CPLD
  • XC95144 - XC95144 In-System Programmable CPLD
  • XC95108 - XC95108 In-System Programmable CPLD
  • XC9500XL - High-Performance CPLD
  • XC95216 - XC95216 In-System Programmable CPLD
  • XC95288 - XC95288 In-System Programmable CPLD
  • XC95288XL - High Performance CPLD
  • XC95288XV - High-Performance CPLD

Full PDF Text Transcription

Click to expand full text
0 R XC95144XL High Performance CPLD DS056 (v2.0) April 3, 2007 00 Features • 5 ns pin-to-pin logic delays • System frequency up to 178 MHz • 144 macrocells with 3,200 usable gates • Available in small footprint packages - 100-pin TQFP (81 user I/O pins) - 144-pin TQFP (117 user I/O pins) - 144-CSP (117 user I/O pins) - Pb-free available for all packages • Optimized for high-performance 3.3V systems - Low power operation - 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals - 3.3V or 2.5V output capability - Advanced 0.
Published: |