CLA80000 High Density CMOS Gate Arrays

Zarlink Semiconductor

Description

( DataSheet : www.DataSheet4U.com ) CLA80000 Series High Density CMOS Gate Arrays DS3820 ISSUE 2.1 July 1997 INTRODUCTION The CLA80k gate array s.

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Datasheet Specifications

Part number: CLA80000
Manufacturer: Zarlink Semiconductor
File Size: 440.92 KB
Datasheet: CLA80000_ZarlinkSemiconductor.pdf
Description: High Density CMOS Gate Arrays

Features

* I I I I I I I I I I 0.7µ (0.8µ drawn) process Typical gate delay 210ps Accurate simulation delay (multi platform support) Support for industry standard workstations Comprehensive cell library 3V option for low power operation Split rail operation (optional 5V I/O, 3V core logic) Low skew clock distr

Applications

* which require assembly in conformance with MIL STD 883. Triple Layer Metal Arrays (High Density Pads) Array type CLT81XXX CLT82XXX CLT83XXX CLT84XXX CLT85XXX CLT86XXX CLT87XXX CLT88XXX CLT89XXX Array elements 2816 8736 17920 30784 54720 100048 157872 307568 513136 Usable gates 1680 5200 10700 18000

CLA80000 Distributors

📁 Related Datasheet

CLA80E1200HF CLA80MT1200NHB CLA80MT1200NHR CLA CLA-EP17 CLA100E1200HB

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CLA80000 High Density CMOS Gate Arrays Zarlink Semiconductor

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