* I I I I I I I I I I 0.7µ (0.8µ drawn) process Typical gate delay 210ps Accurate simulation delay (multi platform support) Support for industry standard workstations Comprehensive cell library 3V option for low power operation Split rail operation (optional 5V I/O, 3V core logic) Low skew clock distr
CLA80000 Datasheet (440.92 KB)
CLA80000
Zarlink Semiconductor
440.92 KB
High density cmos gate arrays.
( DataSheet : www.DataSheet4U.com ) CLA80000 Series High Density CMOS Gate Arrays DS3820 ISSUE 2.1 July 1997 INTRODUCTION The CLA80k gate array s.
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