* I Low power, 0.5µW/MHz/gate at 3V supply (NAND 2 loads) I High density of 5,425 available gates/mm2 I 3V and 5V I/O capability on the same device I 150ps gate delay for 2-input NAND with two loads (5V) I Accurate delay modelling for gates and tracks with sign off quality CAE design libraries for Qui
CLA90000 Datasheet (458.15 KB)
CLA90000
Zarlink Semiconductor
458.15 KB
High density cmos gate arrays.
( DataSheet : www.DataSheet4U.com )
CLA90000 Series
High Density CMOS Gate Arrays
DS5500
ISSUE 2.0
April 1997
INTRODUCTZarlinkION
The CLA90000 fa.
📁 Related Datasheet
CLA90 DIGITAL OUTPUT HIGH VOLTAGE AXIAL LEAD ISOLATORS (ETC)
CLA90AA DIGITAL OUTPUT HIGH VOLTAGE AXIAL LEAD ISOLATORS (ETC)
CLA Thin Film Eight Resistor Array (Vishay Intertechnology)
CLA Silicon Limiter Diode Chips (Alpha Industries)
CLA-EP17 CLA-EP17 (Ferroxcube International Holding B.V.)
CLA100E1200HB High Efficiency Thyristor (IXYS)
CLA100E1200KB High Efficiency Thyristor (IXYS)
CLA100PD1200NA High Efficiency Thyristor (IXYS)
CLA101 Four Channel Phototransistor Array (Clairex)
CLA15E1200NPB High Efficiency Thyristor (IXYS)
