CLA90000 Datasheet (Zarlink Semiconductor) - High Density CMOS Gate Arrays

CLA90000, High Density CMOS Gate Arrays

( DataSheet : www.DataSheet4U.com ) CLA90000 Series High Density CMOS Gate Arrays DS5500 ISSUE 2.0 April 1997 INTRODUCTZarlinkION The CLA90000 family of gate arrays from Zarlink Semiconductor consists of 14 ﬁxed-size arrays with the option of building optimized arrays with up to 1.1 million gates.

This family offers low-power, mixed voltage capability and a high density silicon architecture.

The CLA90000 series is easy to use with and without synthesis tools and comes with design utilities

CLA90000 Features

* I Low power, 0.5µW/MHz/gate at 3V supply (NAND 2 loads) I High density of 5,425 available gates/mm2 I 3V and 5V I/O capability on the same device I 150ps gate delay for 2-input NAND with two loads (5V) I Accurate delay modelling for gates and tracks with sign off quality CAE design libraries for Qui