CLA90000 High Density CMOS Gate Arrays

Zarlink Semiconductor

Description

( DataSheet : www.DataSheet4U.com ) CLA90000 Series High Density CMOS Gate Arrays DS5500 ISSUE 2.0 April 1997 INTRODUCTZarlinkION The CLA90000 fa.

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Datasheet Specifications

Part number: CLA90000
Manufacturer: Zarlink Semiconductor
File Size: 458.15 KB
Datasheet: CLA90000_ZarlinkSemiconductor.pdf
Description: High Density CMOS Gate Arrays

Features

* I Low power, 0.5µW/MHz/gate at 3V supply (NAND 2 loads) I High density of 5,425 available gates/mm2 I 3V and 5V I/O capability on the same device I 150ps gate delay for 2-input NAND with two loads (5V) I Accurate delay modelling for gates and tracks with sign off quality CAE design libraries for Qui

Applications

* from low to high volume. Fixed Gate Arrays Typical Utilization of Gates 2-layer metal 9700 14000 26000 33000 42000 63000 75000 102000 117000 134000 151000 169000 188000 230000 3-layer metal 15000 23000 40000 52000 66000 99000 117000 160000 183000 208000 235000 263000 293000 358000 Number of Pads L

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CLA90000 High Density CMOS Gate Arrays Zarlink Semiconductor

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