CLA70000 Datasheet - Zarlink Semiconductor

CLA70000 High Density CMOS Gate Arrays

( DataSheet : www.DataSheet4U.com ) CLA70000 Series High Density CMOS Gate Arrays DS2462 ISSUE 3.1 March 1992 Recent advances in CMOS processing technology and improvements in design architecture have led to the development of a new generation of array-based ASIC products with vastly improved gate integration densities. This family of CLA70000 1 micron CMOS arrays brings considerable advantages to the design of next generation systems combining high performance and high complexity. Overvie.

CLA70000 Features

* Low power channelless arrays from 5,000 to 250,000 available gates (5µ W / gate / MHz) 1 micron (0.8 micron effective) twin well epitaxial process Typical gate delays of 400 ps (NAND2 , Fanout=2) Comprehensive cell library including DSP, JTAG/BIST and compiled

CLA70000_ZarlinkSemiconductor.pdf