* Low power channelless arrays from 5,000 to 250,000 available gates (5µ W / gate / MHz) 1 micron (0.8 micron effective) twin well epitaxial process Typical gate delays of 400 ps (NAND2 , Fanout=2) Comprehensive cell library including DSP, JTAG/BIST and compiled
CLA70000 Datasheet (188.90 KB)
CLA70000
Zarlink Semiconductor
188.90 KB
High density cmos gate arrays.
( DataSheet : www.DataSheet4U.com )
CLA70000 Series
High Density CMOS Gate Arrays
DS2462
ISSUE 3.1
March 1992
Recent advances in CMOS processing .
📁 Related Datasheet
CLA Thin Film Eight Resistor Array (Vishay Intertechnology)
CLA Silicon Limiter Diode Chips (Alpha Industries)
CLA-EP17 CLA-EP17 (Ferroxcube International Holding B.V.)
CLA100E1200HB High Efficiency Thyristor (IXYS)
CLA100E1200KB High Efficiency Thyristor (IXYS)
CLA100PD1200NA High Efficiency Thyristor (IXYS)
CLA101 Four Channel Phototransistor Array (Clairex)
CLA15E1200NPB High Efficiency Thyristor (IXYS)
CLA1A-MKW PLCC4 1 in 1 SMD LED (CREE)
CLA1A-WKW PLCC4 1 in 1 SMD LED (CREE)
