CDCLVD1208 Datasheet (Texas Instruments) - 2:8 Low Additive Jitter LVDS Buffer

CDCLVD1208, 2:8 Low Additive Jitter LVDS Buffer

The CDCLVD1208 clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 8 pairs of differential LVDS clock outputs (OUT0 through OUT7) with minimum skew for clock distribution.

The CDCLVD1208 can accept two clock sources into an input multiplexer.

The inputs can either be LVDS, L

CDCLVD1208 Features

* 1 2:8 Differential Buffer

* Low Additive Jitter: < 300-fs RMS in 10-kHz to 20-MHz

* Low Output Skew of 45 ps (Maximum)

* Universal Inputs Accept LVDS, LVPECL, and LVCMOS

* Selectable Clock Inputs Through Control Pin

* 8 LVDS Outputs, ANSI EIA/TIA-644A