* 1 2:8 Differential Buffer
* Low Additive Jitter: < 300-fs RMS in 10-kHz to 20-MHz
* Low Output Skew of 45 ps (Maximum)
* Universal Inputs Accept LVDS, LVPECL, and LVCMOS
* Selectable Clock Inputs Through Control Pin
* 8 LVDS Outputs, ANSI EIA/TIA-644A
CDCLVD1208 Datasheet (873.51 KB)
CDCLVD1208
873.51 KB
2:8 low additive jitter lvds buffer.
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CDCLVD1208
SCAS899A
* AUGUST 2010
* REVISED .
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