CDCLVD1213 Datasheet (Texas Instruments) - 1:4 Low Additive Jitter LVDS Buffer

CDCLVD1213, 1:4 Low Additive Jitter LVDS Buffer

The CDCLVD1213 clock buffer distributes an input clock to 4 pairs of differential LVDS clock outputs with low additive jitter for clock distribution.

The input can either be LVDS, LVPECL, or CML.

The CDCLVD1213 contains a high performance divider for one output (QD) which can divide the input clock

CDCLVD1213 Features

* 1 1:4 Differential Buffer

* Low Additive Jitter: < 300-fs RMS in 10-kHz to 20- MHz

* Low Output Skew of 20 ps (Maximum)

* Selectable Divider Ratio 1, /2, /4

* Universal Input Accepts LVDS, LVPECL, and CML

* 4 LVDS Outputs, ANSI EIA/TIA-644A Standard C