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CDCLVD1213 1:4 Low Additive Jitter LVDS Buffer

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Description

Product Folder Sample & Buy Technical Documents Tools & Software Support & Community CDCLVD1213 SCAS897A * JULY 2010 * REVISED OC.
The CDCLVD1213 clock buffer distributes an input clock to 4 pairs of differential LVDS clock outputs with low additive jitter for clock distribution.

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Features

* 1 1:4 Differential Buffer
* Low Additive Jitter: < 300-fs RMS in 10-kHz to 20- MHz
* Low Output Skew of 20 ps (Maximum)
* Selectable Divider Ratio 1, /2, /4
* Universal Input Accepts LVDS, LVPECL, and CML
* 4 LVDS Outputs, ANSI EIA/TIA-644A Standard C

Applications

* Telecommunications and Networking
* Medical Imaging
* Test and Measurement Equipment
* Wireless Communications
* General-Purpose Clocking Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) CDCLVD1213 VQFN (16) 3.00 mm × 3.00 mm (1) For all ava

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