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CDCLVD1212 2:12 Low Additive Jitter LVDS Buffer

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Description

Product Folder Order Now Technical Documents Tools & Software Support & Community CDCLVD1212 SCAS901D * SEPTEMBER 2010 * REVISED .
The CDCLVD1212 clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 12 pairs of differential LVDS clock outputs (OUT0 through.

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Features

* 1 2:12 Differential Buffer
* Low Additive Jitter: < 300-fs RMS in 10-kHz to 20-MHz
* Low Output Skew of 35 ps (Maximum)
* Universal Inputs Accept LVDS, LVPECL, and LVCMOS
* Selectable Clock Inputs Through Control Pin
* 12 LVDS Outputs, ANSI EIA/TIA-64

Applications

* Telecommunications and Networking
* Medical Imaging
* Test and Measurement Equipment
* Wireless Communications

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