* 1 2:12 Differential Buffer
* Low Additive Jitter: < 300-fs RMS in 10-kHz to 20-MHz
* Low Output Skew of 35 ps (Maximum)
* Universal Inputs Accept LVDS, LVPECL, and LVCMOS
* Selectable Clock Inputs Through Control Pin
* 12 LVDS Outputs, ANSI EIA/TIA-64
CDCLVD1212 Datasheet (1.10 MB)
CDCLVD1212
1.10 MB
2:12 low additive jitter lvds buffer.
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CDCLVD1212
SCAS901D
* SEPTEMBER 2010
* REVISED .
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