CDCLVD1216 - 2:16 Low Additive Jitter LVDS Buffer
The CDCLVD1216 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to 16 pairs of differential LVDS clock outputs (OUT0, OUT15) with minimum skew for clock distribution.
The CDCLVD1216 can accept two clock sources into an input multiplexer.
The inputs can either be LVDS, LVPECL, o
CDCLVD1216 Features
* 1
* 2:16 Differential Buffer
* Low Additive Jitter:
