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CDCLVD2106 Dual 1:6 Low Additive Jitter LVDS Buffer

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Description

CDCLVD2106 www.ti.com SCAS902B * SEPTEMBER 2010 * REVISED JANUARY 2011 Dual 1:6 Low Additive Jitter LVDS Buffer Check for Samples: C.
The CDCLVD2106 clock buffer distributes two clock inputs (IN0, IN1) to a total of 12 pairs of differential LVDS clock outputs (OUT0, OUT11).

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Features

* 1
* Dual 1:6 Differential Buffer
* Low Additive Jitter:

Applications

* Telecommunications/Networking
* Medical Imaging
* Test and Measurement Equipment
* Wireless Communications

CDCLVD2106 Distributors

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