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DS90C032B LVDS Quad CMOS Differential Line Receiver

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Description

DS90C032B www.ti.com SNLS052C * MARCH 1999 * REVISED APRIL 2013 DS90C032B LVDS Quad CMOS Differential Line Receiver Check for Sampl.
The DS90C032B is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates.

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Features

* 1
* 2 >155.5 Mbps (77.7 MHz) Switching Rates
* Accepts Small Swing (350 mV) Differential Signal Levels
* High Impedance LVDS Inputs with Power Down
* Ultra Low Power Dissipation
* 600 ps Maximum Differential Skew (5V, 25°C)
* 6.0 ns Maximum Propagation

Applications

* requiring ultra low power dissipation and high data rates. The device supports data rates in excess of 155.5 Mbps (77.7 MHz) and uses Low Voltage Differential Signaling (LVDS) technology. The DS90C032B accepts low voltage (350 mV) differential input signals and translates them to CMOS (TTL compatibl

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