74AUP2G80 Datasheet, Flip-flop, nexperia

74AUP2G80 Features

• Flip-flop
• Wide supply voltage range from 0.8 V to 3.6 V
• High noise immunity
• Complies with JEDEC standards:
• JESD8-12 (0.8 V to 1.3 V)
• JESD8-11 (0.

PDF File Details

Part number:

74AUP2G80

Manufacturer:

nexperia ↗

File Size:

274.87kb

Download:

📄 Datasheet

Description:

Low-power dual d-type flip-flop. The 74AUP2G80 provides the dual positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q outpu

74AUP2G80 Application

• Applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.

TAGS

74AUP2G80

nexperia

📁 Related Datasheet

74AUP2G80 - Low-power dual D-type flip-flop (NXP)
.. 74AUP2G80 Low-power dual D-type flip-flop; positive-edge trigger Rev. 01 — 25 August 2006 Product data sheet 1. General descriptio.

74AUP2G86 - Low Power Dual 2-Input EXCLUSIVE Gate (NXP)
74AUP2G86 Low-power dual 2-input EXCLUSIVE-OR gate Rev. 8 — 24 January 2013 Product data sheet 1. General description The 74AUP2G86 provides the d.

74AUP2G86 - DUAL EXCLUSIVE OR GATE (Diodes)
NEW PRODUCT 74AUP2G86 DUAL EXCLUSIVE OR GATE Description Pin Assignments The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low .

74AUP2G86 - Low-power dual 2-input EXCLUSIVE-OR gate (nexperia)
74AUP2G86 Low-power dual 2-input EXCLUSIVE-OR gate Rev. 10 — 7 December 2020 Product data sheet 1. General description The 74AUP2G86 provides the .

74AUP2G00 - Low-power dual 2-input NAND gate (NXP)
74AUP2G00 Low-power dual 2-input NAND gate Rev. 8 — 5 February 2013 Product data sheet 1. General description The 74AUP2G00 provides dual 2-input NA.

74AUP2G00 - DUAL NAND GATE (Diodes)
NEW PRODUCT 74AUP2G00 DUAL NAND GATE Description Pin Assignments The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power an.

74AUP2G00 - Low-power dual 2-input NAND gate (nexperia)
74AUP2G00 Low-power dual 2-input NAND gate Rev. 11 — 9 June 2022 Product data sheet 1. General description The 74AUP2G00 provides dual 2-input NAND .

74AUP2G00-Q100 - Low-power dual 2-input NAND gate (nexperia)
74AUP2G00-Q100 Low-power dual 2-input NAND gate Rev. 2 — 9 June 2022 Product data sheet 1. General description The 74AUP2G00-Q100 provides dual 2-in.

74AUP2G02 - DUAL NOR GATE (Diodes)
NEW PRODUCT 74AUP2G02 DUAL NOR GATE Description Pin Assignments The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power and.

74AUP2G02 - Low-power Dual 2-input NOR Gate (NXP)
74AUP2G02 Low-power dual 2-input NOR gate Rev. 7 — 4 February 2013 Product data sheet 1. General description The 74AUP2G02 provides a dual 2-input N.