CY7C131E Datasheet

Cypress

CY7C131E

Key Features

True dual-ported memory cells, which allow simultaneous reads of the same memory location
1K/2K × 8 organization
0.35 micron complementary metal oxide semiconductor (CMOS) for optimum speed and power
High speed access: 15 ns
Low operating power: ICC = 110 mA (typical), Standby: ISB3 = 0.05 mA (typical)
Fully asynchronous operation
Automatic power-down
BUSY output flag to indicate access to the same location by both ports
INT flag for port-to-port communication
Available in 52-pin plastic leaded chip carrier (PLCC), 52-pin plastic quad flat package (PQFP)

Part Number	Manufacturer	Description
CY7C1311CV18	Cypress	18-Mb QDRTM-II SRAM 4-Word Burst Architecture
CY7C1312BV18	Cypress	1.8V Synchronous Pipelined SRAM
CY7C1311BV18	Cypress	18-Mb QDRTM-II SRAM 4-Word Burst Architecture
CY7C1318KV18	Cypress	18-Mbit DDR II SRAM Two-Word Burst Architecture
CY7C1313KV18	Cypress	18-Mbit QDR II SRAM Four-Word Burst Architecture
CY7C1315KV18	Cypress	18-Mbit QDR II SRAM Four-Word Burst Architecture
CY7C1312KV18	Cypress	18-Mbit QDR II SRAM Two-Word Burst Architecture
CY7C1314KV18	Cypress	18-Mbit QDR II SRAM Two-Word Burst Architecture
CY7C1311AV18	Cypress	18-Mb QDRTM-II SRAM 4-Word Burst Architecture
CY7C1315AV18	Cypress	18-Mb QDRTM-II SRAM 4-Word Burst Architecture