74AC11 Datasheet | Specifications & PDF Download

MC74AC11, MC74ACT11 co Triple 3-Input t AND Gate • Outputs Source/Sink 24 mA • ′ACT11 Has TTL Compatible Inputs m w w w .D VCC 14 13 12 11 10 9

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TECHNICAL DATA www.DataSheet4U.com KK74AC11 Triple 3-Input AND Gate High-Performance Silicon-Gate CMOS The KK74AC11 is identical in pinout to the L

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HD74AC112/HD74ACT112 Dual JK Negative Edge-Triggered Flip-Flop Description The HD74AC112/HD74ACT112 features individual J, K, Clock and asynchronous

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HD74AC112/HD74ACT112 Dual JK Negative Edge-Triggered Flip-Flop REJ03D0244–0200Z (Previous ADE-205-364 (Z)) Rev.2.00 Jul.16.2004 Description The HD74A

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ăą • Flow-Through Architecture Optimizes PCB Layout • Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise • EPIC (Enhanced-Perf

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CD54AC112, CD74AC112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS325 – JANUARY 2003 D AC Types Feature 1.5-V to 5.5-V Opera

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54AC11002, 74AC11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES • Flow-Through Architecture Optimizes PCB Layout • Center-Pin VCC and GND Configuration Min

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www.ti.com FEATURES • Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise • EPIC™ (Enhanced-Performance Implanted CMOS) 1-µm Pro

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74AC11 — Triple 3-Input AND Gate 74AC11 Triple 3-Input AND Gate Features ■ ICC reduced by 50% ■ Outputs source/sink 24mA January 2008 General Descri

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TC74AC11P/F/FN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74AC11P,TC74AC11F,TC74AC11FN Triple 3-Input AND Gate The TC74AC11 is an a

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TECHNICAL DATA www.DataSheet4U.com KK74AC112 Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS The KK74AC112 is identical in pinou

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• Applications Include: Buffer/Storage Registers, Shift Registers, Pattern Generators • Flow-Through Architecture Optimizes PCB Layout • Center-Pin VC

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74AC11008 QUADRUPLE 2-INPUT POSITIVE-AND GATE D Flow-Through Architecture Optimizes PCB Layout D Center-Pin VCC and GND Configurations Minimize High-

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74AC11240 OCTAL BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS SCAS448A – MAY 1987 – REVISED APRIL 1996 D Flow-Through Architecture Optimizes PCB Layout D C

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74AC11004 HEX INVERTER D Flow-Through Architecture Optimizes PCB Layout D Center-Pin VCC and GND Configuration Minimizes High-Speed Switching Noise D

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• Flow-Through Architecture Optimizes PCB Layout • Center-Pin VCC and GND Configuration Minimizes High-Speed Switching Noise • EPIC™ (Enhanced-Perform

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ą 74AC11258 QUADRUPLE 2ĆLINE TO 1ĆLINE DATA SELECTOR/MULTIPLEXER WITH 3ĆSTATE OUTPUTS SCAS063A − D3257, JANUARY 1989 − REVISED APRIL 1993 • 3-State O

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74AC11239 DUAL 2–LINE TO 4–LINE DECODER/DEMULTIPLEXER • Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems • Incorpor

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