74AC11 Datasheet | Specifications & PDF Download

TC74AC11P/F TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74AC11P, TC74AC11F Triple 3-Input AND Gate The TC74AC11 is an advanced high

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TC74AC11P/F/FN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74AC11P,TC74AC11F,TC74AC11FN Triple 3-Input AND Gate The TC74AC11 is an a

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TC74AC11P/F TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74AC11P, TC74AC11F Triple 3-Input AND Gate The TC74AC11 is an advanced high

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• Generates Either Odd or Even Parity for Nine Data Lines • Cascadable for n-Bits Parity • Direct Bus Connection for Parity Generation or for Checking

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• Contains Six D-Type Flip-Flops • Clock Enable Latched to Avoid False Clocking • Applications Include: Buffer/Storage Registers, Shift Registers, Pat

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74AC11138 3ĆLINE TO 8ĆLINE DECODER/DEMULTIPLEXER D Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems D Incorporates

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74AC11032 QUADRUPLE 2-INPUT POSITIVE-OR GATE D Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise D EPIC™ (Enhanced-Performanc

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www.DataSheet4U.net 74AC11 TRIPLE 3-INPUT AND GATE PRELIMINARY DATA s s s s s s s s s HIGH SPEED: tPD = 4 ns (TYP.) at VCC = 5V LOW POWER DIS

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74AC11 — Triple 3-Input AND Gate 74AC11 Triple 3-Input AND Gate Features ■ ICC reduced by 50% ■ Outputs source/sink 24mA January 2008 General Descri

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• Independent Registers for A and B Buses • Multiplexed Real-Time and Stored Data • Inverting Data Paths • Flow-Through Architecture Optimizes PCB Lay

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• Contains Four Flip-Flops with Double-Rail Outputs • Clock Enable Latched to Avoid False Clocking • Applications Include: Buffer/Storage Registers, S

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D Eight Latches in a Single Package D 3-State Bus-Driving True Outputs D Full Parallel Access for Loading D Buffered Control Inputs D Flow-Through Arc

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ăą • 8-Line to 1-Line Multiplexers Can Perform as Boolean Function Generators, Parallel-to-Serial Converters, or Data Source Selectors • Flow-Through

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• Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators • Flow-Through Architecture to Optimize PCB Layout • Multiple Cent

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ăą • Independent Registers for A and B Buses • Multiplexed Real-Time and Stored Data • Flow-Through Architecture Optimizes PCB Layout • Center-Pin VCC

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ą 74AC11898 10ĆBIT PARALLELĆOUT SERIAL SHIFT REGISTER ą SCAS143 − OCTOBER 1990 − REVISED APRIL 1993 • AND-Gated (Enable/Disable) Serial Inputs • Full

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