74ACT11 Datasheet | Specifications & PDF Download

MC74AC11, MC74ACT11 co Triple 3-Input t AND Gate • Outputs Source/Sink 24 mA • ′ACT11 Has TTL Compatible Inputs m w w w .D VCC 14 13 12 11 10 9

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TECHNICAL DATA www.DataSheet4U.com KK74ACT11 Triple 3-Input AND Gate High-Performance Silicon-Gate CMOS The KK74ACT11 is identical in pinout to the

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HD74AC112/HD74ACT112 Dual JK Negative Edge-Triggered Flip-Flop REJ03D0244–0200Z (Previous ADE-205-364 (Z)) Rev.2.00 Jul.16.2004 Description The HD74A

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TECHNICAL DATA www.DataSheet4U.com KK74ACT112 Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS The KK74ACT112 is identical in pin

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HD74AC112/HD74ACT112 Dual JK Negative Edge-Triggered Flip-Flop Description The HD74AC112/HD74ACT112 features individual J, K, Clock and asynchronous

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TECHNICAL DATA IN74ACT112 Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS The IN74ACT112 is identical in pinout to the LS/ALS112,

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CD54ACT112, CD74ACT112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS323 – JANUARY 2003 D Inputs Are TTL-Voltage Compatible D

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TECHNICAL DATA IN74ACT11 Triple 3-Input AND Gate High-Performance Silicon-Gate CMOS The IN74ACT11 is identical in pinout to the LS/ALS11, HC/HCT11.

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ą • Inputs Are TTL-Voltage Compatible • Contains Eight D-Type Flip-Flops • Clock Enable Latched to Avoid False Clocking • Applications Include: Buffer

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ą • Eight Latches in a Single Package • 3-State Bus-Driving Inverting Outputs • Full Parallel Access for Loading • Buffered Control Inputs • Inputs Ar

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74ACT11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET SCAS064A – D3339, JUNE 1989 – REVISED APRIL 1993 • Inputs Are TTL-Voltage

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ą • Compares Two 8-Bit Words • Inputs Are TTL-Voltage Compatible • Flow-Through Architecture Optimizes PCB Layout • Center-Pin VCC and GND Configurat

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74ACT11593 8-BIT BINARY COUNTER WITH PARALLEL-INPUT REGISTERS AND 3-STATE OUTPUTS SCAS203 – JUNE 1992 – REVISED APRIL 1993 • Inputs Are TTL-Voltage C

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ą • Inputs Are TTL-Voltage Compatible • Local Bus-Latch Capability • Flow-Through Architecture to Optimize PCB Layout • Center-Pin VCC and GND Configu

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• Bidirectional Bus Transceiver in High-Density 24-Pin Package • Inputs Are TTL-Voltage Compatible • Flow-Through Architecture to Optimize PCB Layout

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ą 74ACT11648 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3ĆSTATE OUTPUTS SCAS115 − D3458, MARCH 1990 − REVISED APRIL 1993 • Inputs Are TTL-Voltage Compat

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ą • Local Bus-Latch Capability • Inputs Are TTL-Voltage Compatible • Flow-Through Architecture Optimizes PCB Layout • Center-Pin VCC and GND Configura

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