74AC10 • 74ACT10 Triple 3-Input NAND Gate Novem.
74ACT11011 - TRIPLE 3-INPUT POSITIVE-AND GATES
54ACT11011, 74ACT11011 TRIPLE 3-INPUT POSITIVE-AND GATES • Inputs Are TTL-Voltage Compatible • Flow-Through Architecture Optimizes PCB Layout • Cente.74ACT11109 - DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
54ACT11109, 74ACT11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCAS451 – FEBRUARY 1987 – REVISED APRIL 1993 • Inputs Are TT.74ACT11027 - TRIPLE 3-INPUT POSITIVE-NOR GATES
• Inputs Are TTL-Voltage Compatible • Flow-Through Architecture Optimizes PCB Layout • Center-Pin VCC and GND Configurations Minimize High-Speed Switc.74ACT11352 - DUAL 4-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER
74ACT11352 DUAL 4–LINE TO 1–LINE DATA SELECTOR/MULTIPLEXER • Inputs Are TTL-Voltage Compatible • Permit Multiplexing From N Lines to 1 Line • Perform.74ACT11534 - Octal D-Type EDGE-Triggered Flip-Flop
ą 54ACT11534, 74ACT11534 OCTAL DĆTYPE EDGEĆTRIGGERED FLIPĆFLOPS WITH 3ĆSTATE OUTPUTS SCAS038A − D2957, JULY 1987 − REVISED APRIL 1993 • Eight D-Type .74ACT11821 - 10-BIT BUS-INTERFACE FLIP-FLOPS
• Inputs Are TTL-Voltage Compatible • Provides Extra Data Width Necessary for Wider Address/Data Paths or Buses With Parity • Flow-Through Architectur.74ACT11138 - 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
54ACT11138, 74ACT11138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCAS050A – D3266, JANUARY 1989 – REVISED APRIL 1993 • Designed Specifically for High.74ACT11157 - Quadruple 2-Line to 1-Line Data Selector/Multiplexer
ą 74ACT11157 QUADRUPLE 2ĆLINE TO 1ĆLINE DATA SELECTOR/MULTIPLEXER ą SCAS180 − D3908, SEPTEMBER 1991 − REVISED APRIL 1993 • Inputs Are TTL-Voltage Com.74ACT11238 - 3-Line to 8-Line Decoder/DeMultiplexer
ą • Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems • Noninverting Version of ′ACT11138 • Incorporates 3 Enable Inp.74ACT11470 - 8-Bit Registered Bus Transceivers
ą • Inputs Are TTL-Voltage Compatible • Flow-Through Architecture Optimizes PCB Layout • Center-Pin VCC and GND Configuration Minimizes High-Speed Swi.74ACT11533 - Octal D-Type Transparent Latches
ą • Eight Latches in a Single Package • 3-State Bus-Driving Inverting Outputs • Full Parallel Access for Loading • Buffered Control Inputs • Inputs Ar.74ACT11590 - 8-Bit Binary Counter
ą • Inputs Are TTL-Voltage Compatible • Parallel Registered Outputs • Internal Counters Have Direct Clear • Flow-Through Architecture Optimizes PCB La.74ACT11620 - Octal Bus Transceiver
ą • Inputs Are TTL-Voltage Compatible • Local Bus-Latch Capability • Flow-Through Architecture to Optimize PCB Layout • Center-Pin VCC and GND Configu.74ACT11651 - OCTAL BUS TRANSCEIVER/REGISTER
• Inputs Are TTL-Voltage Compatible • Bus Transceivers/Registers • Independent Registers and Enables for A and B Buses • Multiplexed Real-Time and Sto.74ACT11873 - DUAL 4-BIT D-TYPE LATCH
• Inputs Are TTL-Voltage Compatible • 3-State Buffer-Type Outputs Drive Bus Lines Directly • Bus-Structured Pinout • Flow-Through Architecture to Opti.SN74ACT11PW - TRIPLE 3-INPUT POSITIVE-AND GATE
D 4.5-V to 5.5-V VCC Operation D Inputs Accept Voltages to 5.5 V SN54ACT11 . . . J OR W PACKAGE SN74ACT11 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW).