74ALV Matched Datasheet

Part Number Description Manufacture
Low-Voltage 16-Bit Buffer/Line Driver

• 1.65 V to 3.6 V VCC Supply Operation
• 3.6 V Tolerant Inputs and Outputs
• 26 W Series Resistors in Outputs
• tPD ♦ 3.8 ns max for 3.0 V to 3.6 V VCC ♦ 4.3 ns max for 2.3 V to 2.7 V VCC ♦ 7.6 ns max for 1.65 V to 1.95 V VCC
• Power−off High Impedan
ON Semiconductor
Low-Voltage 16-Bit Buffer
mA Drive at 3.0 V ±12 mA Drive at 2.3 V ±4 mA Drive at 1.65 V
• Supports Live Insertion and Withdrawal
• Includes Active Bushold to Hold Unused or Floating Inputs at a Valid Logic State
• IOFF Specification Guarantees High Impedance When VCC = 0 V†
ON Semiconductor
16-bit transparent D-type latch
two latch enables (1LE and 2LE) and two output enables (1OE and 2OE), each controlling 8-bits. When nLE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its correspondi
Low-Voltage 1.8/2.5/3.3V 16-Bit Buffer
When VCC = 0 V†
• Near Zero Static Supply Current in All Three Logic States (40 mA) Substantially Reduces System Power Requirements
• Latchup Performance Exceeds ±250 mA @ 125°C
• ESD Performance: Human Body Model 2000 V; Machine Model 200 V
• Seco
ON Semiconductor
Low-Voltage 1.8/2.5/3.3V 16-Bit Transparent Latch
able (OEn) inputs. When OE is LOW, the outputs are enabled. When OE is HIGH, the standard outputs are in the high impedance state, but this does not interfere with new data entering into the latches.
• Designed for Low Voltage Operation: VCC = 1.65−3
ON Semiconductor
Dual D-type flip-flop
and benefits
• Wide supply voltage range from 1.65 V to 3.6 V
• Complies with JEDEC standard:
• JESD8-7 (1.65 to 1.95 V)
• JESD8-5 (2.3 to 2.7 V)
• JESD8B (2.7 to 3.6 V)
• 3.6 V tolerant inputs/outputs
• CMOS low power consumption
• Direct interface
16-bit dual supply translating transceiver
and benefits
 5 V tolerant inputs/outputs for interfacing with 5 V logic
 Wide supply voltage range:  3 V port (VCC(A)): 1.5 V to 3.6 V  5 V port (VCC(B)): 1.5 V to 5.5 V
 CMOS low power consumption
 Direct interface with TTL levels
 Control i
16-bit Universal Bus Driver with 3-state Outputs

• VCC = 2.3 V to 3.6 V
• Typical VOL ground bounce 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot 2.0 V (@VCC = 3.3 V, Ta = 25°C)
• High output current ±24 mA (@VCC = 3.0 V)
• Bus hold on data inputs eliminates the need for external pul
Hitachi Semiconductor
20-bit buffer/line driver
and benefits
• CMOS low power consumption
• MultiByte flow-through standard pin-out architecture
• Low inductance multiple VCC and GND pins for minimum noise and ground bounce
• Direct interface with TTL levels (2.7 V to 3.6 V)
• Bus hold on data in
Low Voltage Quad 2-Input NAND Gate
s 1.65V to 3.6V VCC supply operation s 3.6V tolerant inputs and outputs s tPD 3.8 ns max for 3.0V to 3.6V VCC 4.6 ns max for 2.3V to 2.7V VCC 8.2 ns max for 1.65V to 1.95V VCC s Power-off high impedance inputs and outputs s Uses patented Quiet Series
Fairchild Semiconductor

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