74F10 Datasheet | Specifications & PDF Download

MC54/74F109 DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP The MC54/74F109 consists of two high-speed, completely independent transition clocked JK flip-fl

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MC54/74F10 TRIPLE 3-INPUT NAND GATE TRIPLE 3-INPUT NAND GATE VCC 14 13 12 11 10 9 8 FAST™ SCHOTTKY TTL J SUFFIX CERAMIC CASE 632-08 1 2 3 4 5 6 7 G

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SN54F109, SN74F109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SDFS047A – MARCH 1987 – REVISED OCTOBER 1993 • Package Options I

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74F1071 18-Bit Undershoot/Overshoot Clamp October 1994 Revised August 1999 74F1071 18-Bit Undershoot/Overshoot Clamp and ESD Protection Device Gener

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54F/74F109 54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop November 1994 54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop General Descript

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74F10 Triple 3-Input NAND Gate April 1988 Revised July 1999 74F10 Triple 3-Input NAND Gate General Description This device contains three independen

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74F1056 8-Bit Schottky Barrier Diode Array December 1993 Revised August 1999 74F1056 8-Bit Schottky Barrier Diode Array General Description The 74F1

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54F 74F10 Triple 3-Input NAND Gate December 1994 54F 74F10 Triple 3-Input NAND Gate General Description This device contains three independent gates

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74F109 Dual JK Positive Edge-Triggered Flip-Flop April 1988 Revised November 1999 74F109 Dual JK Positive Edge-Triggered Flip-Flop General Descripti

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INTEGRATED CIRCUITS 74F10 Triple 3-input NAND gate 74F11 Triple 3-input AND gate Product specification IC15 Data Handbook 1989 Sep 20 Philips Semico

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INTEGRATED CIRCUITS 74F109 Positive J-K positive edge-triggered flip-flops Product specification IC15 Data Handbook 1990 Oct 23 Philips Semiconducto

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• Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs description These devic

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• Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs description These devic

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SN54F109, SN74F109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SDFS047A – MARCH 1987 – REVISED OCTOBER 1993 • Package Options I

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D Designed to Reduce Reflection Noise D Repetitive Peak Forward Current 300 mA D 8-Bit Array Structure Suited for Bus-Oriented Systems description Thi

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• Designed to Reduce Reflection Noise • Repetitive Peak Forward Current . . . 300 mA • 16-Bit Array Structure Suited for Bus-Oriented Systems descript

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