AT89C51 Datasheet | Specifications & PDF Download

Features • 80C52X2 Core (6 Clocks per Instruction) – Maximum Core Frequency 48 MHz in X1 Mode, 24 MHz in X2 Mode – Dual Data Pointer – Full-duplex Enh

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Features • 80C51 Core Architecture • 256 Bytes of On-chip RAM • 256 Bytes of On-chip XRAM • 16K Bytes of On-chip Flash Memory – Data Retention: 10 Yea

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Features • 80C51 Core Architecture • 256 Bytes of On-chip RAM • 256 Bytes of On-chip XRAM • 16K Bytes of On-chip Flash Memory – Data Retention: 10 Yea

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Features • 80C52 Compatible – 8051 Instruction Compatible – Six 8-bit I/O Ports (64 pins or 68 Pins Versions) – Four 8-bit I/O Ports (44 Pins Version)

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Features • Programmable Audio Output for Interfacing with Common Audio DAC – PCM Format Compatible – I2S Format Compatible • 8-bit MCU C51 Core-based

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AT89C51RD2 / AT89C51ED2 QualPack Qualification Package AT89C51ED2 FLASH 8-bit C51 Microcontroller 64 Kbytes FLASH, 2 Kbytes EEPROM AT89C51RD2 / AT8

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Features • 80C52X2 Core (6 Clocks per Instruction) – Maximum Core Frequency 48 MHz in X1 Mode, 24 MHz in X2 Mode – Dual Data Pointer – Full-duplex Enh

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Features • 80C52 Compatible – 8051 Pin and Instruction Compatible – Four 8-bit I/O ports + 2 I/O 2-wire Interface (TWI) Pins – Three 16-bit Timer/Coun

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Features • MPEG I/II-Layer 3 Hardwired Decoder – Stand-alone MP3 Decoder – 48, 44.1, 32, 24, 22.05, 16 kHz Sampling Frequency – Separated Digital Volu

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Features • 80C52 Compatible – 8051 Instruction Compatible – Four 8-bit I/O Ports (44 Pins Version) – Three 16-bit Timer/Counters – 256 bytes Scratch P

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Features • MPEG I/II-Layer 3 Hardwired Decoder – Stand-alone MP3 Decoder – 48, 44.1, 32, 24, 22.05, 16 kHz Sampling Frequency – Separated Digital Volu

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Features • 80C52 Compatible – 8051 Pin and Instruction Compatible – Four 8-bit I/O Ports – Three 16-bit Timer/Counters – 256 Bytes Scratch Pad RAM – 9

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Features • Compatible with MCS®-51 Products • 32K Bytes of Reprogrammable Flash Memory • Endurance: 10,000 Write/Erase Cycles • 4V to 5.5V Operating R

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Features • 80C52X2 Core (6 Clocks per Instruction) – Maximum Core Frequency 48 MHz in X1 Mode, 24MHz in X2 Mode – Dual Data Pointer – Full-duplex Enha

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Features • Compatible with MCS-51™ Products • 4K Bytes of In-System Reprogrammable Flash Memory – Endurance: 1,000 Write/Erase Cycles • Fully Static O

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Features • 80C52X2 Core (6 Clocks per Instruction) – Maximum Core Frequency 48 MHz in X1 Mode, 24 MHz in X2 Mode – Dual Data Pointer – Full-duplex Enh

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Features • Protocol – USB Used as a Physical Layer – Device Firmware Upgrade Class Compliant – Auto-Frequency Detection • In-System Programming – Read

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Features • 80C52 Compatible – 8051 Pin and Instruction Compatible – Four 8-bit I/O Ports – Three 16-bit Timer/Counters – 256 Bytes Scratch Pad RAM – 9

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Features • MPEG I/II-Layer 3 Hardwired Decoder – Stand-alone MP3 Decoder – 48, 44.1, 32, 24, 22.05, 16 kHz Sampling Frequency – Separated Digital Volu

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Features • 80C51 Core Architecture • 256 Bytes of On-chip RAM • 2048 Bytes of On-chip ERAM • 64K Bytes of On-chip Flash Memory – Data Retention: 10 Ye

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