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AS6C2016 - 128K X 16 BIT LOW POWER CMOS SRAM
FEBRUARY 2008 January 2007 AS6C2016 512K X 8CMOS BIT LOW 128K X 16 BIT LOW POWER SRAMPOWER CMOS SRAM FEATURES Fast access time : 55ns Low power cons.P1822 - (P1818 - P1822) Low Power Mobile VGA EMI Reduction IC
www.DataSheet4U.com Production March 2003 ® P1818/19/20/21/22 Low Power Mobile VGA EMI Reduction IC Features • • • • FCC approved method of EMI a.AS7C513B - 5V 32K x 16 CMOS SRAM
March 2004 AS7C513B ® 5V 32K×16 CMOS SRAM Features • Industrial and commercial temperature • Organization: 32,768 words × 16 bits • Center power an.AS4C1M16E5 - 5V 1M x 16 CMOS DRAM
$XJXVW $6&0 ( 9 0î &026 '5$0 ('2 )HDWXUHV • Organization: 1,048,576 words × 16 bits • High speed - 45/50/60 ns RAS access time - 20.ASM5I23S08A - 3.3V Zero Delay Buffer
www.DataSheet4U.com September 2005 rev 1.4 ASM5P23S08A 3.3V ‘SpreadTrak’ Zero Delay Buffer General Features • • • • Zero input - output propagation.ASM1233D-L - voltage supervisors
www.DataSheet4U.com March 2005 rev 1.3 ASM1233D-L/D/M Low Power, 5V/3.3V, µP Reset, Active LOW, Open-Drain Output Applications • • • • • • • Set-top.ASM161 - uP Supervisory Circuit
www.DataSheet4U.com October 2003 rev 1.0 ASM161 / ASM162 µP Supervisory Circuit Key Features monitor power supplies in • • • • • • Edge triggered ma.P1819 - (P1818 - P1822) Low Power Mobile VGA EMI Reduction IC
www.DataSheet4U.com Production March 2003 ® P1818/19/20/21/22 Low Power Mobile VGA EMI Reduction IC Features • • • • FCC approved method of EMI a.ASM5I23S09A - (ASM5I23S05A / ASM5I23S09A) 3.3V SpreadTrak Zero Delay Buffer
August 2004 rev 2.0 3.3V ‘SpreadTrak’ Zero Delay Buffer General Features 10 MHz to 133- MHz operating range, compatible with CPU and PCI bus fre.ASM5I9350 - 3.3V 1:10 LVCMOS PLL Clock Generator
July 2005 rev 0.2 3.3V 1:10 LVCMOS PLL Clock Generator Features Output frequency range: 25 MHz to 200 MHz Input frequency range: 6.25 MHz to 31..ASM5I9775A - 14-Output Zero Delay Buffer
June 2005 rev 0.3 2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer General Features Output frequency range: 8.3MHz to 200M.ASM8P18S42 - (ASM8x184x) Voltage Mode PWM Controller
June 2005 rev 0.6 ASM8P18S42 / ASM8P18S42ER ASM8P1843 / ASM8P18S43ER ASM8P18S44ER / ASM8P18S45ER Voltage Mode PWM Controller with EMI Reduction Gene.AS7C251MPFD32A - (AS7C251MPFD32A / AS7C251MPFD36A) 2.5V 1M x 32/36 pipelined burst synchronous SRAM
February 2005 ® AS7C251MPFD32A AS7C251MPFD36A 2.5V 1M × 32/36 pipelined burst synchronous SRAM Features • Organization: 1,048,576 words × 32 or 36 b.AS7C251MPFS36A - (AS7C251MPFS32A / AS7C251MPFS36A) 2.5V 1M x 32/36 pipelined burst synchronous SRAM
February 2005 ® AS7C251MPFS32A AS7C251MPFS36A 2.5V 1M × 32/36 pipelined burst synchronous SRAM Features • Organization: 1,048,576 words × 32 or 36 b.ASM4SSTVF32852 - DDR 24-Bit to 48-Bit Registered Buffer
August 2004 rev 2.0 DDR 24-Bit to 48-Bit Registered Buffer ASM4SSTVF32852 Features Differential clock signals. Supports SSTL_2 class II specific.ASM4SSTVF16859 - DDR 13-Bit to 26-Bit Registered Buffer
August 2004 rev 2.0 DDR 13-Bit to 26-Bit Registered Buffer ASM4SSTVF16859 off. Note that RESETB should be supported with a Features Differentia.AS7C33128FT36B - (AS7C33128FT32B / AS7C33128FT36B) 3.3V 128K x 32/36 Flow Through Synchronous SRAM
February 2005 ® AS7C33128FT32B AS7C33128FT36B 3.3V 128K × 32/36 Flow Through Synchronous SRAM Features • • • • • • • Organization: 131,072 words × 3.AS7C33128PFD36A - (AS7C33128PFD32A / AS7C33128PFD36A) 3.3V 128K X 32/36 pipeline burst synchronous SRAM
March 2001 ® AS7C33128PFD32A AS7C33128PFD36A 3.3V 128K × 32/36 pipeline burst synchronous SRAM Features • Organization: 131,072 words × 32 or 36 bit.AS7C33128PFS36B - (AS7C33128PFS32B / AS7C33128PFS36B) 3.3V 128K X 32/36 pipeline burst synchronous SRAM
March 2002 ® AS7C33128PFS32A AS7C33128PFS36A 3.3V 128K X 32/36 pipeline burst synchronous SRAM Features • Organization: 131,072 words × 32 or 36 bit.ASM3P2669A - Low Power Peak EMI Reducing Solution
September 2005 www.DataSheet4U.com rev 1.6 ASM3P2669A Low Power Peak EMI Reducing Solution Features Generates an EMI optimized clock.