Differential-to-3.3V Datasheet | Specifications & PDF Download

MC100LVEP111 2.5V / 3.3V 2:1:10 Differential ECL/PECL/HSTL Clock Driver Description The MC100LVEP111 is a low skew 2:1:10 differential driver, design

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NB3N111K 3.3V Differential 1:10 Fanout Clock Driver with HCSL Outputs Description The NB3N111K is a differential 1:10 Clock fanout buffer with High−s

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NB6L239 2.5V / 3.3V Any Differential Clock IN to Differential LVPECL OUT ÷1/2/4/8, ÷2/4/8/16 Clock Divider Description The NB6L239 is a high−speed, l

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m o .c 4U 2.5V / 3.3V tMultilevel Input to e Differential e LVPECL/LVNECL h Clock or S Data a t Receiver/Driver/Translator a Buffer .D w The NB6L16 is

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NBSG16VS 2.5V/3.3V SiGe Differential Receiver/Driver with Variable Output Swing Description The NBSG16VS is a differential receiver/driver targeted f

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www.DataSheet4U.com Integrated Circuit Systems, Inc. ICS8432I-101 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER FEATURES • Dual differen

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Low Skew, 1-to-6, Crystal/ LVCMOS/ Differential-to-3.3V, 2.5V LVPECL Fanout Buffer ICS8536-01 DATA SHEET GENERAL DESCRIPTION The ICS8536-01 is a lo

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FIN1026 3.3V LVDS 2-Bit High Speed Differential Receiver June 2002 Revised June 2002 FIN1026 3.3V LVDS 2-Bit High Speed Differential Receiver Genera

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Integrated Circuit Systems, Inc. ICS84329 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER FEATURES • Fully integrated P

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SY100ELT22L 3.3V Dual LVTTL-to-Differential LVPECL Translator Features • 3.3V Power Supply • 300 ps Typical Propagation Delay • <100 ps Output-to-Out

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DS90LV047A 3V LVDS Quad CMOS Differential Line Driver July 1999 DS90LV047A 3V LVDS Quad CMOS Differential Line Driver General Description The DS90LV

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NB3N1200K, NB3W1200L 3.3 V 100/133 MHz Differential 1:12 HCSL or Push-Pull Clock ZDB/Fanout Buffer for PCle Description The NB3N1200K and NB3W1200L d

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Micrel 5V/3.3V DIFFERENTIAL DATA AND CLOCK D FLIP-FLOP WITH SET AND RESET ECL Pro™ SY10EP53V SY10EP53V FINAL ECL Pro™ FEATURES s s s s 3.3V and 5V

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NB3N108K 3.3V Differential 1:8 Fanout Clock Data Driver with HCSL Outputs Description The NB3N108K is a differential 1:8 Clock fanout buffer with Hig

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700MHz, Low Jitter, Crystal-to-3.3V Differential LVPECL Frequency Synthesizer 84330-02 Data Sheet PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXP

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DS26LV32AT 3V Enhanced CMOS Quad Differential Line Receiver April 1999 DS26LV32AT 3V Enhanced CMOS Quad Differential Line Receiver General Descripti

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MC10EP451, MC100EP451 3.3V / 5V ECL 6-Bit Differential Register with Master Reset Description The MC10/100EP451 is a 6−bit fully differential registe

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NBSG53A 2.5 V/3.3 V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider with Reset and OLS* The NBSG53A is a multi-function differe

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NB6LQ572 2.5V / 3.3V Differential 4:1 Mux w/Input Equalizer to 1:2 LVPECL Clock/Data Fanout / Translator Multi−Level Inputs w/ Internal Termination Th

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