CY7C1522V18 architecture equivalent, 72-mbit ddr-ii sio sram 2-word burst architecture.
* 72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36)
* 300-MHz clock for high bandwidth
* 2-Word burst for reducing address bus frequency
* Double Data Ra.
The CY7C1522V18, CY7C1529V18, CY7C1523V18, CY7C1524V18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II SIO (Double Data Rate Separate I/O) architecture. The DDR-II SIO consists of two separate ports to access the memory array. The Read port.
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