* Double-data-rate architecture; two data transfers per clock cycle
* The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture
*.

512M bits DDR SDRAM

EDD5116AGTA-LI

EDD5116AGTA

EDD5116ADTA

EDD5116ADTA-E

EDD5116ADTA-LI

EDD5116AFTA

EDD5116AFTA-5

EDD5104ABTA

EDD5104ADTA

EDD5104ADTA-E

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