EDD5116AGTA - 512M bits DDR SDRAM

This page provides the datasheet information for the EDD5116AGTA, a member of the EDD5108AGTA 512M bits DDR SDRAM family.

Features

Double-data-rate architecture; two data transfers per clock cycle.
The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture.
Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver.
Data inputs, outputs, and DM are synchronized with DQS.
DQS is edge-aligned with data for READs; centeraligned with data for WRITEs.
Differential clock inputs (CK and /CK).
DLL.

Elpida Memory

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Datasheet Details

Part number	EDD5116AGTA
Manufacturer	Elpida Memory
File Size	575.84 KB
Description	512M bits DDR SDRAM
Datasheet	EDD5116AGTA Datasheet
Additional preview pages of the EDD5116AGTA datasheet.

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Full PDF Text Transcription

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DATA SHEET 512M bits DDR SDRAM EDD5108AGTA (64M words × 8 bits) EDD5116AGTA (32M words × 16 bits) Specifications • Density: 512M bits • Organization ⎯ 16M words × 8 bits × 4 banks (EDD5108AGTA) ⎯ 8M words × 16 bits × 4 banks (EDD5116AGTA) • Package: 66-pin plastic TSOP (II) ⎯ Lead-free (RoHS compliant) • Power supply: VDD, VDDQ = 2.5V ± 0.2V • Data rate: 400Mbps/333Mbps/266Mbps (max.) • Four internal banks for concurrent operation • Interface: SSTL_2 • Burst lengths (BL): 2, 4, 8 • Burst type (BT): ⎯ Sequential (2, 4, 8) ⎯ Interleave (2, 4, 8) • /CAS Latency (CL): 2, 2.5, 3 • Precharge: auto precharge option for each burst access • Driver strength: normal/weak • Refresh: auto-refresh, self-refresh • Refresh cycles: 8192 cycles/64ms ⎯ Average refresh period: 7.

Published: Nov 20, 2009 |