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Elpida Memory

EDS5104ABTA Datasheet Preview

EDS5104ABTA Datasheet

512M bits SDRAM

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PRELIMINARY DATA SHEET
512M bits SDRAM
EDS5104ABTA (128M words × 4 bits)
EDS5108ABTA (64M words × 8 bits)
EDS5116ABTA (32M words × 16 bits)
Description
Pin Configurations
The EDS5104AB is a 512M bits SDRAM organized as
33,554,432 words × 4 bits × 4 banks. The EDS5108AB
is a 512M bits SDRAM organized as 16,777,216 words
× 8 bits × 4 banks. The EDS5116AB is a 512M bits
SDRAM organized as 8,388,608 words × 16 bits × 4
banks. All inputs and outputs are referred to the rising
edge of the clock input. It is packaged in standard 54-
pin plastic TSOP (II).
Features
3.3V power supply
Clock frequency: 166MHz/133MHz (max.)
LVTTL interface
Single pulsed /RAS
4 banks can operate simultaneously and
independently
Burst read/write operation and burst read/single write
operation capability
Programmable burst length (BL): 1, 2, 4, 8, full page
2 variations of burst sequence
Sequential (BL = 1, 2, 4, 8, full page)
Interleave (BL = 1, 2, 4, 8)
Programmable /CAS latency (CL): 2, 3
Byte control by DQM
: DQM (EDS5104AB, EDS5108AB)
: UDQM, LDQM (EDS5116AB)
Refresh cycles: 8192 refresh cycles/64ms
2 variations of refresh
Auto refresh
Self refresh
/xxx indicates active low signal.
54-pin TSOP
VDD VDD VDD
NC DQ0 DQ0
VDDQ VDDQ VDDQ
NC NC DQ1
DQ0 DQ1 DQ2
VSSQ VSSQ VSSQ
NC NC DQ3
NC DQ2 DQ4
VDDQ VDDQ VDDQ
NC NC DQ5
DQ1 DQ3 DQ6
VSSQ VSSQ VSSQ
NC NC DQ7
VDD VDD VDD
NC NC LDQM
/WE /WE /WE
/CAS /CAS /CAS
/RAS /RAS /RAS
/CS /CS /CS
BA0 BA0 BA0
BA1 BA1 BA1
A10 A10 A10
A0 A0 A0
A1 A1 A1
A2 A2 A2
A3 A3 A3
VDD VDD VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54 VSS VSS VSS
53 DQ15 DQ7 NC
52 VSSQ VSSQ VSSQ
51 DQ14 NC NC
50 DQ13 DQ6 DQ3
49 VDDQ VDDQ VDDQ
48 DQ12 NC NC
47 DQ11 DQ5 NC
46 VSSQ VSSQ VSSQ
45 DQ10 NC NC
44 DQ9 DQ4 DQ2
43 VDDQ VDDQ VDDQ
42 DQ8 NC NC
41 VSS VSS VSS
40 NC NC NC
39 UDQM DQM DQM
38 CLK CLK CLK
37 CKE CKE CKE
36 A12 A12 A12
35 A11 A11 A11
34 A9 A9 A9
33 A8 A8 A8
32 A7 A7 A7
31 A6 A6 A6
30 A5 A5 A5
29 A4 A4 A4
28 VSS VSS VSS
X 16
X8
X4
(Top view)
A0 to A12, Address input
BA0, BA1 Bank select address
DQ0 to DQ15 Data-input/output
/CS Chip select
/RAS
Row address strobe
/CAS
Column address strobe
/WE Write enable
DQM
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
Input/output mask
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0250E10 (Ver. 1.0)
Date Published March 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2002




Elpida Memory

EDS5104ABTA Datasheet Preview

EDS5104ABTA Datasheet

512M bits SDRAM

No Preview Available !

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA
Ordering Information
Part number
Mask
Version
Organization
(words × bits)
EDS5104ABTA-6B
EDS5104ABTA-7A
EDS5104ABTA-75*
B
128M × 4
EDS5108ABTA-6B
EDS5108ABTA-7A
EDS5108ABTA-75*
64M × 8
EDS5116ABTA-6B
EDS5116ABTA-7A
EDS5116ABTA-75*
32M × 16
Note: 100MHz operation at /CAS latency = 2.
Internal Banks
4
Part Number
Clock frequency
MHz (max.)
166
133
133
166
133
133
166
133
133
/CAS latency
3
2, 3
3
3
2, 3
3
3
2, 3
3
Package
54-pin Plastic
TSOP (II)
E D S 51 04 A B TA - 6B
Elpida Memory
Material Type
D: Mono
Function
S: SDRAM
Density & Bank
51: 512M/4 Banks
Bit Organization
04: x4
08: x8
16: x16
Interface
A: 3.3V, LVTTL
Mask Revision
Package
TA: TSOP (II)
Speed
6B: 166MHz/CL3
7A: 133MHz/CL2, 3
75: 133MHz/CL3
100MHz/CL2
Preliminary Data Sheet E0250E10 (Ver. 1.0)
2


Part Number EDS5104ABTA
Description 512M bits SDRAM
Maker Elpida Memory
Total Page 30 Pages
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