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ICS87004I Datasheet

Differential-to-LVCMOS/LVTTL Zero Delay Clock Generator

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1:4, Differential-to-LVCMOS/LVTTL
Zero Delay Clock Generator
ICS87004I
DATA SHEET
General Description
The ICS87004I is a highly versatile 1:4 Differential-
ICS to-LVCMOS/LVTTL Clock Generator. The ICS87004I
HiPerClockS™ has two selectable clock inputs. The CLK0, nCLK0
and CLK1, nCLK1 pairs can accept most standard
differential input levels. Internal bias on the nCLK0 and
nCLK1 inputs allows the CLK0 and CLK1 inputs to accept
LVCMOS/LVTTL. The ICS87004I has a fully integrated PLL and can
be configured as a zero delay buffer, multiplier or divider and has an
input and output frequency range of 15.625MHz to 250MHz. The
reference divider, feedback divider and output divider are each
programmable, thereby allowing for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external
feedback allows the device to achieve “zero delay” between the input
clock and the output clocks. The PLL_SEL pin can be used to
bypass the PLL for system test and debug purposes. In bypass
mode, the reference clock is routed around the PLL and into the
internal output dividers.
Features
Four LVCMOS/LVTTL outputs, 7typical output impedance
Selectable CLK0/nCLK0 or CLK1/nCLK1 clock inputs
CLKx/nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
Internal bias on nCLK0 and nCLK1 to support LVCMOS/LVTTL
levels on CLK0 and CLK1 inputs
Output frequency range: 15.625MHz to 250MHz
Input frequency range: 15.625MHz to 250MHz
VCO range: 250MHz to 500MHz
External feedback for “zero delay” clock regeneration with
configurable frequencies
Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
Fully integrated PLL
Cycle-to-cycle jitter: 45ps (maximum)
Output skew: 65ps (maximum)
Static phase offset: 50ps ± 150ps (3.3V ± 5%), CLK0/nCLK0
Full 3.3V or 2.5V output operating supply
5V tolerant
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Block Diagram
Pin Assignment
PLL_SEL Pullup
CLK0 Pulldown
nCLK0 Pullup/Pulldown
CLK1 Pulldown
nCLK1 Pullup/Pulldown
CLK_SEL Pulldown
FB_IN Pulldown
0
1
÷2, ÷4, ÷8, ÷16
÷32, ÷64, ÷128
PLL
0
1
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
Q0
Q1
Q2
Q3
GND
Q0
VDDO
SEL0
SEL1
SEL2
SEL3
CLK_SEL
VDD
CLK0
nCLK0
GND
1
2
3
4
5
6
7
8
9
10
11
12
24 Q1
23 VDDO
22 Q2
21 GND
20 Q3
19 VDDO
18 MR
17 FB_IN
16 PLL_SEL
15 CLK1
14 nCLK1
13 VDDA
ICS87004I
SEL0 Pulldown
SEL1 Pulldown
24-Lead TSSOP
7.8mm x 4.4mm x 0.925mm package body
G Package
Top View
SEL2 Pulldown
SEL3 Pulldown
MR Pulldown
ICS87004AGI REVISION D JANUARY 4, 2010
1
©2009 Integrated Device Technology, Inc.


Integrated Device Technology Electronic Components Datasheet

ICS87004I Datasheet

Differential-to-LVCMOS/LVTTL Zero Delay Clock Generator

No Preview Available !

ICS87004I Data Sheet
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Table 1. Pin Descriptions
Number
1, 12, 21
2, 20,
22, 24
3, 19, 23
4, 5,
6, 7
8
9
10
11
13
14
15
16
17
18
Name
GND
Q0, Q3,
Q2, Q1
VDDO
SEL0, SEL1,
SEL2, SEL3
CLK_SEL
VDD
CLK0
nCLK0
VDDA
nCLK1
CLK1
PLL_SEL
FB_IN
MR
Type
Power
Output
Power
Description
Power supply ground.
Single-ended clock outputs. 7typical output impedance.
LVCMOS/LVTTL interface levels.
Output supply pins.
Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
Input
Power
Input
Input
Power
Input
Input
Input
Input
Input
Pulldown
Pulldown
Pullup/
Pulldown
Pullup/
Pulldown
Pulldown
Pullup
Pulldown
Pulldown
Clock select input. When HIGH, selects differential CLK1, nCLK1. When LOW,
selects differential CLK0, nCLK0. LVCMOS/LVTTL interface levels.
Core supply pin.
Non-inverting differential clock input.
Inverting differential clock input. VDD/2 default when left floating.
Analog supply pin.
Inverting differential clock input. VDD/2 default when left floating.
Non-inverting differential clock input.
PLL select. Selects between the PLL and reference clock as the input to the
dividers. When LOW, selects the reference clock (PLL Bypass). When HIGH,
selects PLL (PLL Enabled). LVCMOS/LVTTL interface levels.
Feedback input to phase detector for regenerating clocks with “Zero Delay.”
Connect to one of the outputs. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the outputs to go low. When logic LOW, the internal dividers and the
outputs are enabled. LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN Input Capacitance
RPULLUP
Input Pullup Resistor
RPULLDOWN Input Pulldown Resistor
CPD
Power Dissipation
Capacitance (per output)
ROUT
Output Impedance
Test Conditions
VDD, VDDO = 3.465V
VDD, VDDO = 2.625V
Minimum
Typical
4
51
51
57
Maximum
23
17
12
Units
pF
k
k
pF
pF
ICS87004AGI REVISION D JANUARY 4, 2010
2
©2009 Integrated Device Technology, Inc.


Part Number ICS87004I
Description Differential-to-LVCMOS/LVTTL Zero Delay Clock Generator
Maker IDT
Total Page 15 Pages
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