ICS87004I Datasheet | IDT

Description The ICS87004I is a highly versatile 1:4 Differential- ICS to-LVCMOS/LVTTL Clock Generator. The ICS87004I Hi Per Clock S™ has two selectable clock inputs. The CLK0, n CLK0 and CLK1, n CLK1 pairs can accept most standard differential input levels. Internal bias on the n CLK0 and n CLK1 inputs allows the CLK0 and CLK1 inputs to accept LVCMOS/LVTTL. The ICS87004I has a fully integrated PLL and can be configured as a zero delay buffer, multiplier or divider and has an input and output frequency range of 15.625MHz to 250MHz. The reference divider, feedback divider and output divider are each programmable, thereby allowing for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve “zero delay” between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers. Features - Four LVCMOS/LVTTL outputs, 7Ω typical output impedance - Selectable CLK0/n CLK0 or CLK1/n CLK1 clock inputs - CLKx/n CLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL - Internal bias on n CLK0 and n CLK1 to support LVCMOS/LVTTL levels on CLK0 and CLK1 inputs - Output frequency range: 15.625MHz to 250MHz - Input frequency range: 15.625MHz to 250MHz - VCO range: 250MHz to 500MHz - External feedback for “zero delay” clock regeneration with configurable frequencies - Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 - Fully integrated PLL - Cycle-to-cycle jitter: 45ps (maximum) - Output skew: 65ps (maximum) - Static phase offset: 50ps ± 150ps (3.3V ± 5%), CLK0/n CLK0 - Full 3.3V or 2.5V output operating supply - 5V tolerant - -40°C to 85°C ambient operating temperature - Available in both standard (Ro HS 5) and lead-free (Ro HS 6) packages Block...