KM736V795 Datasheet | Samsung Semiconductor

FEATURES - Synchronous Operation. - 2 Stage Pipelined operation with 4 Burst. - On-Chip Address Counter. - Self-Timed Write Cycle. - On-Chip Address and Control Registers. - VDD= 3.3V+0.3V/-0.165V Power Supply. - I/O Supply Voltage 2.5V+0.4V/-0.13V. - 5V Tolerant Inputs Except I/O Pins. - Byte Writable Function. - Global Write Enable Controls a full bus-width write. - Power Down State via ZZ Signal. - LBO Pin allows a choice of either a interleaved burst or a linear burst. - Three Chip Enables for simple depth expansion with No Data Contention ; 2cycle Enable, 1cycle Disable. - Asynchronous Output Enable Control. - ADSP, ADSC, ADV Burst Control Pins. - TTL-Level Three-State Output. - 100-TQFP-1420A GENERAL DESCRIPTION The KM736V795 is a 4,718,592-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System. It is organized as 128K words of 36bits and integrates address and control registers, a 2-bit burst address counter and added some new functions for high performance cache RAM applications; GW, BW, LBO, ZZ. Write cycles are internally self-timed and synchronous. Full bus-width write is done by GW, and each byte write is performed by the bination of WEx and BW when GW is high. And with CS1 high, ADSP is blocked to control signals. Burst cycle can be initiated with either the address status processor(ADSP) or address status cache controller(ADSC) inputs. Subsequent...