Datasheet Summary
Document Title
128Kx36 Synchronous SRAM
128Kx36-Bit Synchronous Pipelined Burst SRAM
Revision History
Rev. No.
0.0 0.1
History
Initial draft Change DC characteristics VDD condition from VDD=3.3V+10%/-5% Change Input/output leackage currant from ±1µA to ±2µA Modify Read timing & Power down cycle timing. Change ISB2 value from 30mA to 20mA. Remove DC characteristics ISB1
- L ver.& ISB2
- L ver . Remove Low power version. Change Undershoot spec from -3.0V(pulse width≤20ns) to -2.0V(pulse width≤tCYC/2) Add Overshoot spec 4.6V((pulse width≤tCYC/2) Change VIN max from 5.5V to VDD+0.5V
Draft Date
February. 02. 1998 February. 12. 1998
Remark
Preliminary Preliminary
April. 14....