KM736V787 Document Title 128Kx36-Bit Synchronous Burst SRAM 128Kx36 Synchronous SRAM Revision History Rev.
No.
0.0 0.1 History Initial draft Modify power down cycle timing & Interleaved read timing, Insert Note 4 at AC timing characteristics.
Change ISB1 value from 10mA to 30mA.
Change ISB2 value from 10mA to 20mA.
Change Undershoot spec from -3.0V(pulse width≤20ns) to -2.0V(pulse width≤tCYC/2) Add Overshoot spec 4.6V((pulse width≤tCYC/2) Change VIH max from 5.5V to VDD+0.5V Change ISB2 value