128kx36/x32 & 256kx18 synchronous sram.
* Synchronous Operation.
* On-Chip Address Counter.
* Self-Timed Write Cycle.
* On-Chip Address and Control Registers.
* 3.3V+0.165V/-0.165V Power Sup.
GW, BW, LBO, ZZ. Write cycles are internally self-timed and synchronous. Full bus-width write is done by GW, and each b.
The K7B163625A and K7B161825A are 18,874,368-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System. It is organized as 512K(1M) words of 36(32/18) bits and integrates address.
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