K7B403625M Datasheet (Samsung semiconductor) - 128Kx36-Bit Synchronous Burst SRAM

K7B403625M, 128Kx36-Bit Synchronous Burst SRAM

K7B403625M Document Title 128Kx36-Bit Synchronous Burst SRAM 128Kx36 Synchronous SRAM Revision History Rev.

No.

History Draft Date 0.0 Initial draft May.

15.

1997 0.1 Modify power down cycle timing & Interleaved read timing, Insert Note 4 at AC timing characteristics.

Change ISB1 value from 10mA to 30mA.

Change ISB2 value from 10mA to 20mA.

Feb.

11.

1998 0.2 Change Undershoot spec from -3.0V(pulse width≤20ns) to -2.0V(pulse width≤tCYC/2) Add Overshoot spec 4.6V((pulse width≤tCYC/2) Chan