(km736v887 / km718v987) 256kx36 & 512kx18 synchronous sram.
* Synchronous Operation.
* On-Chip Address Counter.
* Self-Timed Write Cycle.
* On-Chip Address and Control Registers.
* 3.3V+0.165V/-0.165V Power Sup.
GW, BW, LBO, ZZ. Write cycles are internally self-timed and synchronous. Full bus-width write is done by GW, and each b.
The KM736V887 and KM718V987 are 9,437,184-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System. It is organized as 256K(512K) words of 36(18) bits and integrates address and.
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