TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
4 GBIT (512M 8 BIT) CMOS NAND E2PROM
The TH58BVG2S3HBAI4 is a single 3.3V 4 Gbit (4,429,185,024 bits) NAND Electrically Erasable and
Programmable Read-Only Memory (NAND E2PROM) organized as (2048 64) bytes 64 pages 4096 blocks.
The device has a 2112-byte static register which allows program and read data to be transferred between the
register and the memory cell array in 2112-bytes increments. The Erase operation is implemented in a single block
unit (128 Kbytes 4 Kbytes: 2112 bytes 64 pages).
The TH58BVG2S3HBAI4 is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed making
the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other systems which require high-density non-volatile memory data storage.
The TH58BVG2S3HBAI4 has ECC logic on the chip and 8bit read errors for each 528Bytes can be corrected
Memory cell array
2112 128K 8 x 2
(128K 4K) bytes
Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy,
Multi Page Read, Multi Page Program, Multi Block Erase, ECC Status Read
Number of valid blocks
Min 4016 blocks
Max 4096 blocks
VCC 2.7V to 3.6V
Cell array to register 40 s typ. (Single Page Read) / 55us typ. (Multi Page Read)
Serial Read Cycle
25 ns min (CL=50pF)
Auto Page Program
Auto Block Erase
330 s/page typ.
2.5 ms/block typ.
Read (25 ns cycle)
30 mA max.
30 mA max
30 mA max
100 A max
P-TFBGA63-0911-0.80CZ (Weight: 0.154 g typ.)
8bit ECC for each 528Byte is implemented on the chip.