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TH58100FTI Datasheet - Toshiba Semiconductor

TH58100FTI TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

The TH58100 is a single 3.3 V 1-Gbit (1,107,296,256) bit NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as 528 bytes × 32 pages × 8192 blocks. The device has a 528-byte static register which allows program and read data to be transferred between the register and.

TH58100FTI Features

* Organization Memory cell allay 528 × 128K × 8 × 2 Register 528 × 8 Page size 528 bytes Block size (16K + 512) bytes Modes Read, Reset, Auto Page Program Auto Block Erase, Status Read Multi Block Program, Multi Block Erase Mode control Serial input/output Command control

TH58100FTI_ToshibaSemiconductor.pdf

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Datasheet Details

Part number:

TH58100FTI

Manufacturer:

Toshiba ↗ Semiconductor

File Size:

495.96 KB

Description:

Tentative toshiba mos digital integrated circuit silicon gate cmos.

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TH58100FTI TH58100FTI TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS Toshiba Semiconductor

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