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ZL30117 - SONET/SDH Low Jitter Line Card Synchronizer

Description

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Features

  • Synchronizes with standard telecom system references and synthesizes a wide variety of protected telecom line interface clocks that are compliant with Telcordia GR-253-CORE and ITU-T G.813 Internal APLL provides standard output clock frequencies from 6.48 MHz up to 622.08 MHz with jitter less than 1 ps RMS for OC-48/STM-16 interfaces Programmable output synthesizer generates clock frequencies from any multiple of 8 kHz up to 77.76 MHz in addition to 2 kHz Digital Phase Locked-Loop (DPL.

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Datasheet Details

Part number ZL30117
Manufacturer Zarlink Semiconductor
File Size 303.88 KB
Description SONET/SDH Low Jitter Line Card Synchronizer
Datasheet download datasheet ZL30117 Datasheet

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Full PDF Text Transcription

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www.DataSheet4U.com ZL30117 SONET/SDH Low Jitter Line Card Synchronizer Data Sheet February 2006 A full Design Manual is available to qualified customers. To register, please send an email to TimingandSync@Zarlink.com. Ordering Information ZL30117GGG 64 Pin CABGA Trays ZL30117GGG2 64 Pin CABGA* Trays *Pb Free Tin/Silver/Copper -40oC to +85oC • Provides 3 reference inputs which support clock frequencies with any multiples of 8 kHz up to 77.
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