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ZL30119 - Low Jitter Line Card Synchronizer

Description

12 1.1 DPLL

Features

  • Ordering Information June 2006.
  • Synchronizes with standard telecom system references and synthesizes a wide variety of protected telecom line interface clocks that are compliant with Telcordia GR-253-CORE and ITU-T G.813.
  • Internal APLL provides standard output clock frequencies up to 622.08 MHz that meet jitter requirements for interfaces up to OC-192/STM-64.
  • Programmable output synthesizers (P0, P1) generate clock frequencies from any multiple of 8 kHz up to 77.76.

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Datasheet preview – ZL30119

Datasheet Details

Part number ZL30119
Manufacturer Zarlink Semiconductor
File Size 353.28 KB
Description Low Jitter Line Card Synchronizer
Datasheet download datasheet ZL30119 Datasheet
Additional preview pages of the ZL30119 datasheet.

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Full PDF Text Transcription

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ZL30119 SONET/SDH OC-48/OC-192 Line Card Synchronizer Data Sheet Features Ordering Information June 2006 • Synchronizes with standard telecom system references and synthesizes a wide variety of protected telecom line interface clocks that are compliant with Telcordia GR-253-CORE and ITU-T G.813 • Internal APLL provides standard output clock frequencies up to 622.08 MHz that meet jitter requirements for interfaces up to OC-192/STM-64 • Programmable output synthesizers (P0, P1) generate clock frequencies from any multiple of 8 kHz up to 77.
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