CDCLVD2106 datasheet, buffer equivalent, Texas Instruments

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CDCLVD2106 Features and benefits

1
* Dual 1:6 Differential Buffer
* Low Additive Jitter: <300 fs rms in 10 kHz
– 20 MHz
* Low Within Bank Output Skew of 45 ps (Max)
* Univ.

CDCLVD2106 Application

* Telecommunications/Networking
* Medical Imaging
* Test and Measurement Equipment
* Wireless Communicat.

CDCLVD2106 Description

The CDCLVD2106 clock buffer distributes two clock inputs (IN0, IN1) to a total of 12 pairs of differential LVDS clock outputs (OUT0, OUT11). Each buffer block consists of one input and 6 LVDS outputs. The inputs can either be LVDS, LVPECL, or LVCMOS..

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