CDCLVD2106 Overview
The CDCLVD2106 clock buffer distributes two clock inputs (IN0, IN1) to a total of 12 pairs of differential LVDS clock outputs (OUT0, OUT11). Each buffer block consists of one input and 6 LVDS outputs. The inputs can either be LVDS, LVPECL, or LVCMOS.
CDCLVD2106 Key Features
- Dual 1:6 Differential Buffer
- Low Additive Jitter: <300 fs rms
- 20 MHz
- Low Within Bank Output Skew of 45 ps (Max)
- Universal Inputs Accept LVDS, LVPECL
- One Input Dedicated for Six Outputs
- Total of 12 LVDS Outputs, ANSI EIA/TIA-644A
- Clock Frequency up to 800 MHz
- 2.375-2.625 V Device Power Supply
- Industrial Temperature Range -40°C to 85°C