CY7C1315BV18, CY7C1311BV18 Datasheet - Cypress Semiconductor

CY7C1315BV18 (CY7C1x1xBV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture

The CY7C1311BV18, CY7C1911BV18, CY7C1313BV18, and CY7C1315BV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write po.

CY7C1315BV18 Features

* Separate Independent Read and Write data ports

* Supports concurrent transactions

* 300-MHz clock for high bandwidth

* 4-Word Burst for reducing address bus frequency

* Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 600 M

CY7C1311BV18_CypressSemiconductor.pdf

CY7C1315BV18 Datasheet Preview — This datasheet PDF includes multiple part numbers: CY7C1315BV18, CY7C1311BV18. Please refer to the document for exact specifications by model.

Datasheet Details

Part number:

CY7C1315BV18, CY7C1311BV18

Manufacturer:

Cypress Semiconductor

File Size:

529.85 KB

Description:

(cy7c1x1xbv18) 18-mb qdrtm-ii sram 4-word burst architecture.

Note:

This datasheet PDF includes multiple part numbers: CY7C1315BV18, CY7C1311BV18.
Please refer to the document for exact specifications by model.

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TAGS

CY7C1315BV18 CY7C1311BV18 CY7C1x1xBV18 18-Mb QDRTM-II SRAM 4-Word Burst Architecture Cypress Semiconductor

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