CY7C1315BV18 - (CY7C1x1xBV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
The CY7C1311BV18, CY7C1911BV18, CY7C1313BV18, and CY7C1315BV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture.
QDR-II architecture consists of two separate ports to access the memory array.
The Read port has dedicated Data Outputs to support Read operations and the Write po
CY7C1315BV18 Features
* Separate Independent Read and Write data ports
* Supports concurrent transactions
* 300-MHz clock for high bandwidth
* 4-Word Burst for reducing address bus frequency
* Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 600 M
