CY7C1315JV18 Datasheet - Cypress Semiconductor

CY7C1315JV18 (CY7C1x1xJV18) 18-Mbit QDR II SRAM 4-Word Burst Architecture

The CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support.

CY7C1315JV18 Features

* CY7C1311JV18/CY7C1911JV18 CY7C1313JV18/CY7C1315JV18 ® Configurations CY7C1311JV18

* 2M x 8 CY7C1911JV18

* 2M x 9 CY7C1313JV18

* 1M x 18 CY7C1315JV18

* 512K x 36 Separate Independent Read and Write Data Ports

* Supports concurrent transactions 300 MHz Cloc

CY7C1315JV18 Datasheet (705.07 KB)

CY7C1315JV18 Datasheet Preview — Preview of CY7C1315JV18 PDF

Datasheet Details

Part number:

CY7C1315JV18

Manufacturer:

Cypress Semiconductor

File Size:

705.07 KB

Description:

(cy7c1x1xjv18) 18-mbit qdr ii sram 4-word burst architecture.

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TAGS

CY7C1315JV18 CY7C1x1xJV18 18-Mbit QDR SRAM 4-Word Burst Architecture Cypress Semiconductor

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