CY7C1378B - 9-Mbit (256K x 32) Pipelined SRAM

Product Overview

Cypress Semiconductor

Datasheet Details

Part number	CY7C1378B
Manufacturer	Cypress Semiconductor
File Size	381.57 KB
Description	9-Mbit (256K x 32) Pipelined SRAM
Datasheet	CY7C1378B Datasheet
Additional preview pages of the CY7C1378B datasheet.

Product details

Description

1] The CY7C1378B is a 3.3V, 256K x 32 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states.The CY7C1378B is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle.This feature dramatically improves the throughput of the SRAM, especially in systems that require frequent Write/Read transitions.

Features

Pin compatible and functionally equivalent to ZBT devices.
Internally self-timed output buffer control to eliminate the need to use OE.
Byte Write capability.
256K x 32 common I/O architecture.
Single 3.3V power supply.
Fast clock-to-output times.
3.2 ns (for 200-MHz device).
3.5 ns (for 166-MHz device).
Clock Enable (CEN) pin to suspend operation.
Synchronous self-timed writes.
Asynchronous Outp.

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Published: Jan 25, 2010 |