* No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles
* Supports up to 133 MHz bus operations with zero wait states
* Data is transferred on every clock
* Pin compatible and functionally equivalent to ZBT™ devices
* Internally self timed o
CY7C1463KV33 Datasheet (954.99 KB)
CY7C1463KV33
Cypress Semiconductor
954.99 KB
36-mbit (1m x 36/2m x 18) flow-through sram.
CY7C1461KV33 CY7C1463KV33 36-Mbit (1M × 36/2M × 18) Flow-Through SRAM with NoBL™ Architecture 36-Mbit (1M × 36/2M × 18) Flow-Through SRAM with NoBL™ .
📁 Related Datasheet
CY7C1463AV25 Flow-Through SRAM (Cypress Semiconductor)
CY7C1463AV33 Flow-Through SRAM (Cypress Semiconductor)
CY7C1463BV33 36-Mbit (2 M x 18) Flow-Through SRAM (Cypress Semiconductor)
CY7C146 2K x 8 Dual-Port Static RAM (Cypress Semiconductor)
CY7C1460AV25 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM (Cypress Semiconductor)
CY7C1460AV33 36-Mbit Pipelined SRAM (Cypress Semiconductor)
CY7C1460BV25 36-Mbit (1 M x 36/2 M x 18) Pipelined SRAM (Cypress Semiconductor)
CY7C1460KV25 36-Mbit (1M x 36/2M x 18) Pipelined SRAM (Cypress Semiconductor)
CY7C1460KV33 36-Mbit (1M x 36/2M x 18) Pipelined SRAM (Cypress Semiconductor)
CY7C1460KVE25 36-Mbit (1M x 36/2M x 18) Pipelined SRAM (Cypress Semiconductor)
