CY7C1471BV25 - 72-Mbit (2 M x 36) Flow-Through SRAM
CY7C1471BV25 Features
* No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles
* Supports up to 133 MHz bus operations with zero wait states
* Data transfers on every clock
* Pin compatible and functionally equivalent to ZBT™ devices
* Internally self timed output bu
