* No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles
* Supports up to 133 MHz bus operations with zero wait states
* Data transfers on every clock
* Pin compatible and functionally equivalent to ZBT™ devices
* Internally self timed output bu
CY7C1471BV25 Datasheet (790.90 KB)
CY7C1471BV25
Cypress Semiconductor
790.90 KB
72-mbit (2 m x 36) flow-through sram.
CY7C1471BV25
72-Mbit (2 M × 36) Flow-Through SRAM with NoBL™ Architecture
72-Mbit (2 M × 36/1 M × 72) Flow-Through SRAM with NoBL™ Architecture
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