* No bus latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles
* Supports up to 133 MHz bus operations with zero wait states
* Data is transferred on every clock
* Pin compatible and functionally equivalent to ZBT™ devices
* Internally self timed outp
CY7C1471BV33 Datasheet (648.07 KB)
CY7C1471BV33
Cypress Semiconductor
648.07 KB
72-mbit (2 m x 36/4 m x 18) flow-through sram.
CY7C1471BV33 CY7C1473BV33
72-Mbit (2 M × 36/4 M × 18) Flow-Through SRAM with NoBL™ Architecture
72-Mbit (2 M × 36/4 M × 18) Flow-Through SRAM with No.
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