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CY7C1355A (CY7C1355A / CY7C1357A) 256K x 36/512K x 18 Synchronous Flow-Thru SRAM

CY7C1355A Description

www.DataSheet4U.com CY7C1357A CY7C1355A 256K x 36/512K x 18 Synchronous Flow-Thru SRAM with NoBL™ Architecture .
The CY7C1355A and CY7C1357A SRAMs are designed to eliminate dead cycles when transitions from READ to WRITE or vice versa.

CY7C1355A Features

* Zero Bus Latency, no dead cycles between write and read cycles
* Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns
* Fast clock speed: 133, 117, and 100 MHz
* Fast OE access time: 6.5, 7.0, and 7.5ns
* Internally synchronized registered outputs eliminate the nee

CY7C1355A Applications

* Interleaved or linear four-word burst capability Individual byte write (BWa

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Datasheet Details

Part number
CY7C1355A
Manufacturer
Cypress Semiconductor
File Size
776.64 KB
Datasheet
CY7C1355A_CypressSemiconductor.pdf
Description
(CY7C1355A / CY7C1357A) 256K x 36/512K x 18 Synchronous Flow-Thru SRAM

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📌 All Tags

CY7C1355A CY7C1357A 256K 512K Synchronous Flow-Thru SRAM Cypress Semiconductor
Cypress Semiconductor CY7C1355A-like datasheet