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FIN1032 - 3.3V LVDS 4-Bit High Speed Differential Receiver

Datasheet Summary

Description

This quad receiver is designed for high speed interconnect utilizing Low Voltage Differential Signaling (LVDS) technology.

The receiver translates LVDS levels, with a typical differential input threshold of 100mV, to LVTTL signal levels.

Features

  • s Greater than 400Mbs data rate s 3.3V power supply operation s 0.4ns maximum differential pulse skew s 2.5ns maximum propagation delay s Low power dissipation s Power OFF protection s Fail safe protection for open-circuit, shorted and terminated conditions s Meets or exceeds the TIA/EIA-644 LVDS standard s Pin compatible with equivalent RS-422 and LVPECL devices s 16-Lead SOIC and TSSOP packages save space Ordering Code: Order Number FIN1032M FIN1032MTC Package Number M16A MTC16 Package Descri.

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Datasheet Details

Part number FIN1032
Manufacturer Fairchild Semiconductor
File Size 246.65 KB
Description 3.3V LVDS 4-Bit High Speed Differential Receiver
Datasheet download datasheet FIN1032 Datasheet
Additional preview pages of the FIN1032 datasheet.

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Full PDF Text Transcription

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FIN1032 3.3V LVDS 4-Bit High Speed Differential Receiver August 2001 Revised December 2001 FIN1032 3.3V LVDS 4-Bit High Speed Differential Receiver General Description This quad receiver is designed for high speed interconnect utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100mV, to LVTTL signal levels. LVDS provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed transfer of clock and data. The FIN1032 can be paired with its companion driver, the FIN1031, or any other Fairchild LVDS driver. Features s Greater than 400Mbs data rate s 3.3V power supply operation s 0.4ns maximum differential pulse skew s 2.
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