* VDD, VDDQ = 2.6V +/- 0.1V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional da
HY5DU28422LT Datasheet (560.43 KB)
HY5DU28422LT
Hynix Semiconductor
560.43 KB
(hy5du28xx22d(l)t) 128mb-s ddr sdram.
www.DataSheet4U.com
HY5DU28422D(L)T HY5DU28822D(L)T HY5DU281622D(L)T
128Mb-S DDR SDRAM
HY5DU28422D(L)T HY5DU28822D(L)T HY5DU281622D(L)T
DataSheet4U..
📁 Related Datasheet
HY5DU28422LT (HY5DU28xxxAT) 3rd 128M DDR SDRAM (Hynix Semiconductor)
HY5DU28422AT 3rd 128M DDR SDRAM (Hynix Semiconductor)
HY5DU28422DT (HY5DU28xx22D(L)T) 128Mb-S DDR SDRAM (Hynix Semiconductor)
HY5DU28422T 2nd 128M DDR SDRAM (Hynix Semiconductor)
HY5DU281622 4 Banks x 2M x 16Bit Double Data Rate SDRAM (Hyundai)
HY5DU281622AT (HY5DU28xxxAT) 3rd 128M DDR SDRAM (Hynix Semiconductor)
HY5DU281622AT-6 128M(8Mx16) DDR SDRAM (Hynix Semiconductor)
HY5DU281622DT (HY5DU28xx22D(L)T) 128Mb-S DDR SDRAM (Hynix Semiconductor)
HY5DU281622ET 128M(8Mx16) GDDR SDRAM (Hynix Semiconductor)
HY5DU281622FTP 128Mb DDR SDRAM (Hynix)
