IDT74SSTV16857 Datasheet - IDT

IDT74SSTV16857 14-BIT REGISTERED BUFFER

The SSTV16857 is a 14-bit registered buffer designed for 2.3V-2.7V VDD and supports low standby operation. All data inputs and outputs are SSTL_2 level compatible with JEDEC standard for SSTL_2. RESET is an LVCMOS input since it must operate predictably during the power-up phase. RESET, which can .

IDT74SSTV16857 Features

* 2.3V to 2.7V Operation SSTL_2 Class II style data inputs/outputs Differential CLK input RESET control compatible with LVCMOS levels Flow-through architecture for optimum PCB design Drive up to equivalent of 14 SDRAM lo

IDT74SSTV16857_IDT.pdf