IDT74SSTVF16859 - 13-BIT TO 26-BIT REGISTERED BUFFER
APPLICATIONS: * Along with CSPT857C, Zero Delay PLL Clock buffer, provides complete solution for DDR1 DIMMs FUNCTIONAL BLOCK DIAGRAM 51 RESET CLK CLK 48 49 VREF D1 45 35 1D C1 R 32 Q1B 16 Q1A TO 12 OTHER CHANNELS COMMERCIAL TEMPERATURE RANGE 1 c 2003 Integrated Device Technology
IDT74SSTVF16859 Features
* 1:2 register buffer Meets or exceeds JEDEC standard SSTVF16859 2.3V to 2.7V Operation for PC1600, PC2100, and PC2700 2.5V to 2.7V Operation for PC3200 SSTL_2 Class I style data inputs/outputs Differential CLK
