* l l l l Maximum lead temperature for soldering 1.6 mm (0.062 in.) from case for 10 s l International standard packages Low RDS (on) HDMOSTM process Rugged polysilicon gate cell structure Low package inductance (< 5 nH) - easy to drive and to protect Fast switching times Symbol Test Conditions
IXTH24N50 Datasheet (107.40 KB)
IXTH24N50
IXYS Corporation
107.40 KB
Megamos fet.
MegaMOSTMFET
IXTH / IXTM 21N50 IXTH / IXTM 24N50 N-Channel Enhancement Mode
VDSS 500 V 500 V
ID25
RDS(on)
21 A 0.25 Ω 24 A 0.23 Ω
Symbol VDSS VDG.
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