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Integrated Circuit Systems, Inc.
ICS8735-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
FEATURES
• 5 differential 3.3V LVPECL outputs • Selectable differential clock inputs • CLKx, nCLKx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Output frequency range: 31.25MHz to 700MHz • Input frequency range: 31.25MHz to 700MHz • VCO range: 250MHz to 700MHz • Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 • External feedback for “zero delay” clock regeneration with configurable frequencies • Cycle-to-cycle jitter: 25ps (maximum) • Output skew: 25ps (maximum) • Static phase offset: 50ps ± 100ps • 3.