Description
SY10/100EP451L 3.3V ECL 6-Bit Differential Register with Master Reset General .
The SY10/100EP451L is a 6-bit fully differential register with common clock and single-ended Master Reset (MR).
Features
* 450ps typical propagation delay Maximum frequency > 3.0GHz typical Asynchronous Master Reset 20ps skew within device, 35ps skew device-to-device PECL mode operating range:
* VCC = 3.0V to 3.6V with VEE
Applications
* where a registered data path is necessary. All inputs have an internal 75k Ω pull-down resistor. Differential inputs have an override clamp. Unused differential register inputs can be left open and will default LOW. When the differential inputs are forced to < VEE +1.2V, the clamp will override and
