74AUP2G38 Datasheet - NXP

74AUP2G38, Low Power Dual 2-Input NAND Gate

www.DataSheet4U.com 74AUP2G38 Low-power dual 2-input NAND gate (open-drain) Rev.01 * 16 October 2006 Product data sheet 1.General descript.
The 74AUP2G38 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

74AUP2G38_PhilipsSemiconductors.pdf

74AUP2G38 Datasheet Preview — Preview of 74AUP2G38 PDF

Datasheet Details

Part number:

74AUP2G38

Manufacturer:

NXP ↗

File Size:

128.95 KB

Description:

Low Power Dual 2-Input NAND Gate

Features

* I Wide supply voltage range from 0.8 V to 3.6 V I High noise immunity I Complies with JEDEC standards: N JESD8-12 (0.8 V to 1.3 V) N JESD8-11 (0.9 V to 1.65 V) N JESD8-7 (1.2 V to 1.95 V) N JESD8-5 (1.8 V to 2.7 V) N JESD8-B (2.7 V to 3.6 V) I ESD protection: N HBM JESD22-A114-D Class 3A exceeds 500

Applications

* using IOFF. The IOFF circuitry disables the output, preventing the damaging backﬂow current through the device when it is powered down. The 74AUP2G38 provides the dual 2-input NAND gate with open-drain output. The output of the device is an open drain and can be connected to other open-drain outputs

74AUP2G38 Distributors

📁 Related Datasheet

74AUP2G32 74AUP2G34 74AUP2G3404 74AUP2G3407 74AUP2G00-Q100 74AUP2G02

📌 All Tags

74AUP2G38 Low Power Dual 2-Input NAND Gate NXP

NXP 74AUP2G38-like datasheet