SSTUA32864 Datasheet (NXP) - configurable registered buffer

SSTUA32864, configurable registered buffer

The SSTUA32864 is a 25-bit 1 : 1 or 14-bit 1 : 2 conﬁgurable registered buffer designed for 1.7 V to 2.0 V VDD operation.

All clock and data inputs are compatible with the JEDEC standard for SSTL_18.

The control inputs are LVCMOS.

All outputs are 1.8 V CMOS drivers that have been optimized to drive

SSTUA32864 Features

* s s s s s s s s s s s s Conﬁgurable register supporting DDR2 Registered DIMM applications Conﬁgurable to 25-bit 1 : 1 mode or 14-bit 1 : 2 mode Controlled output impedance drivers enable optimal signal integrity and speed Exceeds SSTUA32864 JEDEC speciﬁcation speed performance (1.8 ns max. single-bi